It's a little hard to read your schematic, but I notice a couple of things:
- You are missing the third 1V1 pin on the CPU (pin 50), at least on the schematic. Maybe this is an artifact of your footprint and it is in fact connected? Likewise there should be 9 pins at 3V3 and your schematic only shows 4.
- The connection to ADC2 isn't strictly speaking permitted. Most of the GPIOs are described in the datasheet as "fault tolerant", which really means they are allowed to have signals on them when the chip is powered down. However, the four ADC pins aren't specified that way - they have conventional protection diodes on the pins, so applying a voltage to this pin before the rest of the chip is powered up will attempt to power the chip via the protection diodes.
Finally, I wonder about your layout (just because we've seen lots of boards with odd behaviour posted here which turned out to have really bad layout).
- You are missing the third 1V1 pin on the CPU (pin 50), at least on the schematic. Maybe this is an artifact of your footprint and it is in fact connected? Likewise there should be 9 pins at 3V3 and your schematic only shows 4.
- The connection to ADC2 isn't strictly speaking permitted. Most of the GPIOs are described in the datasheet as "fault tolerant", which really means they are allowed to have signals on them when the chip is powered down. However, the four ADC pins aren't specified that way - they have conventional protection diodes on the pins, so applying a voltage to this pin before the rest of the chip is powered up will attempt to power the chip via the protection diodes.
Finally, I wonder about your layout (just because we've seen lots of boards with odd behaviour posted here which turned out to have really bad layout).
Statistics: Posted by arg001 — Tue Jul 16, 2024 5:21 pm
