Device Tree • Re: RPI5: Issue with GPCLK0 Clock Generation on GPIO4 in ALT0 Mode

First question: Does the RP1 (I mean the HW, not the existing drivers as they are written now) allow to reconfigure one of the clocks derived from pll_audio_core (i.e. synchronous to clk_i2s bclk) to run at e.g. 11,289,600Hz (i.e. 256fs for 44.1kHz, i.e. divider 71 from pll_audio_core) and have one of the GPCLK pins configured to output this clk?

Yes. As long as VCO and divider input maximums are respected. There might be enough plumbing in the clocks framework to just declare parents and clock rates manually in devicetree, and end up with GPCLK sourced from the audio PLL again.

Second question: Please what are the limitations for the pll_audio_core values (i.e. possible non/denom values for the fractional PLL from the 50MHz RP1 xosc)? E.g. 812,851,200Hz would allow generating 45,158,400Hz as well as 22,579,200Hz, the most common MCLK frequencies for the 44.1kHz-family rates.

The 801,800,000Hz for 48kHz seems to use PLL ratio 4009/250 . The 801,561,600Hz for 44.1kHz seems to use 250488 (18bits)/15625 (13bits) which seem quite long-bit values.

Thanks a lot for any info.

Pavel.

It's a fractional-N PLL with a 10.24bit feedback divider and reference predivider of 1-7. The VCO is rated for 600-2400MHz. Preference is given for the lowest VCO that achieves the target output frequency as that consumes the least amount of power.

Statistics: Posted by jdb — Fri Jul 19, 2024 5:14 pm

---