Realistically, turning off SRAM1 will only matter if you go to sleep. See the RP2350 DS to get an estimate.
From 6.2.2. Power States (page 434), SRAM1 power draw is the difference between P0.0 and P0.1. But it would be rather difficult to measure it because its quiescent power (== SRAM1 block not accessed by any other block) is rather small. From 14.9.7.2. Power consumption in Low Power states (page 1331), we can get a ballpark figure using P1.0 and P1.1 -- the quiescent power draw of SRAM1 is about 50 uA. About the same for SRAM0 too. Too small for the USB power dongle to measure.
The principal scenario where shutting down SRAM1 would matter is during the ~10 uA sleep. In a project, you can (1) do everything as quickly as possible, then sleep, or (2) turn down the clocks -- shutting down one or more PLLs saves a lot of power (the board will likely run under 5 mA with both PLLs off and running from the 12 MHz XOSC, still useful speed), or (3) see 8.1.1.1. Low Power Oscillator (page 503) where you can run clk_sys using the LPOSC 32 kHz internal oscillator (can be calibrated to 1%), then speed up on occasion.
Sleeping would require the most time for starting back up, I guess. If you switch clocks and need a PLL for a high-performance task, the PLL needs time to start up. Or you can run the chip very slowly because the low power mode of the internal regulator has a 1 mA limit, see 6.3.1.2. Low Power Mode (page 438), but changing regulator modes (low -> normal) will also take time. So there are plenty of strategies to use or try -- the problem with many very low power strategies is the time taken or latency (PLLs, regulator modes, oscillators, etc all need time to get to normal) before code executes at speed.
(Disclaimer: Only a discussion on DS info, but I would be very interested in tested results, because I don't plan to get RP2350 just yet -- I can't keep up with them product releases anyway)
From 6.2.2. Power States (page 434), SRAM1 power draw is the difference between P0.0 and P0.1. But it would be rather difficult to measure it because its quiescent power (== SRAM1 block not accessed by any other block) is rather small. From 14.9.7.2. Power consumption in Low Power states (page 1331), we can get a ballpark figure using P1.0 and P1.1 -- the quiescent power draw of SRAM1 is about 50 uA. About the same for SRAM0 too. Too small for the USB power dongle to measure.
The principal scenario where shutting down SRAM1 would matter is during the ~10 uA sleep. In a project, you can (1) do everything as quickly as possible, then sleep, or (2) turn down the clocks -- shutting down one or more PLLs saves a lot of power (the board will likely run under 5 mA with both PLLs off and running from the 12 MHz XOSC, still useful speed), or (3) see 8.1.1.1. Low Power Oscillator (page 503) where you can run clk_sys using the LPOSC 32 kHz internal oscillator (can be calibrated to 1%), then speed up on occasion.
Sleeping would require the most time for starting back up, I guess. If you switch clocks and need a PLL for a high-performance task, the PLL needs time to start up. Or you can run the chip very slowly because the low power mode of the internal regulator has a 1 mA limit, see 6.3.1.2. Low Power Mode (page 438), but changing regulator modes (low -> normal) will also take time. So there are plenty of strategies to use or try -- the problem with many very low power strategies is the time taken or latency (PLLs, regulator modes, oscillators, etc all need time to get to normal) before code executes at speed.
(Disclaimer: Only a discussion on DS info, but I would be very interested in tested results, because I don't plan to get RP2350 just yet -- I can't keep up with them product releases anyway)
Statistics: Posted by katak255 — Mon Aug 26, 2024 2:28 am