Hi all,
I am experimenting with mailbox interrupts on the pi4.
I have code that works but I get a spurious mailbox interrupt.
I write to the set register, and in the interrupt handler I first read the mailbox value from the clr register and then write it back to clear it.
Then I move between el0 and el1, then disable the mailbox interrupts, and then go back to el1 and re-enable them.
When I re-enable the mailbox interrupts, a new one gets generated. I read the mailbox value and get the value that I had cleared previously.
My understanding is that by writing to the clr register and zeroing out the mailbox value I would not get other mailbox interrupts before writing again to the set registers.
It looks like some caching issue with the mailbox set/clr registers.
Am I wrong in my understanding? Is there a known way to fix that?
Thank you
I am experimenting with mailbox interrupts on the pi4.
I have code that works but I get a spurious mailbox interrupt.
I write to the set register, and in the interrupt handler I first read the mailbox value from the clr register and then write it back to clear it.
Then I move between el0 and el1, then disable the mailbox interrupts, and then go back to el1 and re-enable them.
When I re-enable the mailbox interrupts, a new one gets generated. I read the mailbox value and get the value that I had cleared previously.
My understanding is that by writing to the clr register and zeroing out the mailbox value I would not get other mailbox interrupts before writing again to the set registers.
It looks like some caching issue with the mailbox set/clr registers.
Am I wrong in my understanding? Is there a known way to fix that?
Thank you
Statistics: Posted by yaw moo — Thu Sep 05, 2024 5:30 am