PIO does have a small delay, that's asymmetric between input and output (but not between 1 and 0) but nothing like as big as you are reporting, so there must be something else going on in your setup.
For the chain that you are measuring: input GPIO -> wait instruction -> out instruction -> output GPIO pin there are the following delays:
- 2 clocks input synchronizer. Can be switched off, but not safe to do so in your case.
- 1 clock input to PIO
- 1 clock execute WAIT instruction
- 1 clock output from PIO
plus analogue propagation delays to the pin (small, and varies from pin to pin)
So you'd expect 5 clocks - 40ns at the default 125MHz - plus on average half a clock between this asynchronous edge to align with the 125MHz clock, plus a couple of ns for analogue delays, so about 45ns.
So your rising edge timing is unexpectedly long, yet your falling edge timing is impossibly short. My first thought, like @gmx, is that your 5V level shifter is asymmetric and if you were measuring at the pins of the RP2040 then it would be symmetric.
For the chain that you are measuring: input GPIO -> wait instruction -> out instruction -> output GPIO pin there are the following delays:
- 2 clocks input synchronizer. Can be switched off, but not safe to do so in your case.
- 1 clock input to PIO
- 1 clock execute WAIT instruction
- 1 clock output from PIO
plus analogue propagation delays to the pin (small, and varies from pin to pin)
So you'd expect 5 clocks - 40ns at the default 125MHz - plus on average half a clock between this asynchronous edge to align with the 125MHz clock, plus a couple of ns for analogue delays, so about 45ns.
So your rising edge timing is unexpectedly long, yet your falling edge timing is impossibly short. My first thought, like @gmx, is that your 5V level shifter is asymmetric and if you were measuring at the pins of the RP2040 then it would be symmetric.
Statistics: Posted by arg001 — Sat Oct 26, 2024 8:45 am