Updating register by set is actually doing a bitwise OR by writing the mask at an offset (+0x2000) address of the register (or alias).Thanks for your answers. So clearly it is better to use the instructions for updating the registers clear, xor and set.
If the instructions clear and xor seem clear to me, updating a register by set seems obscure to me.
I will do some tests to clarify my vision.
From RP2350 datasheet:
Read the whole chapter, there some exceptions.2.1.3. Atomic Register Access
Each peripheral register block is allocated 4 kB of address space, with registers accessed using one of 4 methods,
selected by address decode.
• Addr + 0x0000 : normal read write access
• Addr + 0x1000 : atomic XOR on write
• Addr + 0x2000 : atomic bitmask set on write
• Addr + 0x3000 : atomic bitmask clear on write
This allows software to modify individual fields of a control register without performing a read-modify-write sequence.
Instead, the peripheral itself modifies its contents in-place. Without this capability, it is difficult to safely access IO
registers when an interrupt service routine is concurrent with code running in the foreground, or when the two
processors run code in parallel.
The four atomic access aliases occupy a total of 16 kB. Native atomic writes take the same number of clock cycles as
normal writes. Most peripherals on RP2350 provide this functionality natively, but some peripherals (I2C, UART, SPI and
SSI) add this functionality using a bus interposer. The bus interposer translates upstream atomic writes into
downstream read-modify-write sequences at the boundary of the peripheral, at the cost of additional clock cycles.
Atomic writes that use a bus interposer take two additional clock cycles compared to normal writes.
Statistics: Posted by gmx — Sat Dec 14, 2024 7:44 pm
