Some answer here : https://github.com/foss-for-synopsys-dw ... i/dw_spi.c
And https://github.com/foss-for-synopsys-dw ... spi_priv.h
Where these registers are master only:So no special settings for CS and clock (excepted clock mode), there are just an external CS required for SPI4 slave. I not understand when the CS input is always to "1", I get these interrupts: Transmit FIFO Overflow + Receive FIFO Overflow + Receive FIFO Underflow
And https://github.com/foss-for-synopsys-dw ... spi_priv.h
Where these registers are master only:
Code:
#define CTRL1 (0x01) // master only#define SER (0x04) // master only#define BAUDR (0x05) // master onlyStatistics: Posted by aniplay — Sat Apr 13, 2024 8:52 am