One of my DIY ISA adventures involved analysing the code being compiled, and generating the emulator so unused opcodes were discarded and more frequently used ones got shorter opcodes and could be placed in RAM or in-lined with the emulator loop. The upload to a Pico would be user code plus its emulator.I liked the idea of profiling to find the most commonly used 68000 instructions and then storing the emulation routines for those instructions in RAM to avoid delays resulting from execute in place.
The RISC-V ISA was designed around most frequently used opcodes and making the ISA incredibly easy to decode and execute. The advantages don't fully extend to software emulation because the bit-order encodings for some fields is quite painful.
I have always maintained that the first CPU which has well designed, ideally single cycle, bit-field separation and recombination hardware built-in will likely become first choice for emulation platform.
Statistics: Posted by hippy — Thu Jun 20, 2024 10:42 am